Abstract:

A study on the drop test reliability of 0.5mm pitch lead-free chip scale packages (CSPs) will be discussed.  Fifteen 0.5mm pitch CSPs were assembled on a standard JEDEC drop reliability test board with Sn3.0Ag0.5Cu lead-free solder. Eight boards were edge-bonded with a UV-cured acrylic; eight boards were edge-bonded with a thermal-cured epoxy; and twelve boards were assembled without edge bonding. Half of the edge-bonded test boards were subjected to drop tests at a peak acceleration of 1500G with a pulse duration of 0.5ms, and the other half subjected to drop tests at a peak acceleration of 2900G with a pulse duration of 0.3ms. Half of the test boards without edge bonding were subjected to drop tests at a peak acceleration of 900G with a pulse duration of 0.7ms, and the other half subjected to drop tests at a peak acceleration of 1500G with a pulse duration of 0.5ms.

Two drop test failure detection systems were used in this study to monitor the failure of solder joints: a high-speed resistance measurement system and a post-drop static resistance measurement system. The high-speed resistance measurement system, which has a scan frequency of 50KHz and a 16-bit signal width, is able to detect intermittent failures during the short drop impact duration. Statistics of the number of drops to failure for the 15 component locations on each test board are reported. The effect of component position on drop test reliability is discussed. The test results show that the drop test performance of edge-bonded CSPs is five to eight times better than the CSPs without edge bonding.

Bio:

Andrew Farris is a graduate student pursuing the M. Sc. degree in the Electrical Engineering department of California Polytechnic State University at San Luis Obispo.  He completed his B. Sc. degree in Computer Engineering in 2006, also at Cal Poly.  His interests include digital integrated circuit design, programmable logic devices, computer architecture, electronics reliability, and failure analysis.